Computer Architecture: A Quantitative Approach, 4th Edition

Computer Architecture: A Quantitative Approach, 4th Edition

John L. Hennessy, David A. Patterson

Language: English

Pages: 704

ISBN: 0123704901

Format: PDF / Kindle (mobi) / ePub


The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelism as the key to unlocking the power of multiple processor architectures. Additionally, the new edition has expanded and updated coverage of design topics beyond processor performance, including power, reliability, availability, and dependability.

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Increased coverage on achieving parallelism with multiprocessors.

Case studies of latest technology from industry including the Sun Niagara Multiprocessor, AMD Opteron, and Pentium 4.

Three review appendices, included in the printed volume, review the basic and intermediate principles the main text relies upon.

Eight reference appendices, collected on the CD, cover a range of topics including specific architectures, embedded systems, application specific processors--some guest authored by subject experts.

Pro Git

Automatic Design of Decision-Tree Induction Algorithms (Springer Briefs in Computer Science)

Haptic Human-Computer Interaction

Mathematical Foundations of Parallel Computing

 

 

 

 

 

 

 

 

 

 

 

keep up or disappear. The Digital Equipment Vax could not, and so it was replaced by a RISC architecture. Intel rose to the challenge, primarily by translating x86 (or IA-32) instructions into RISC-like instructions internally, allowing it to adopt many of the innovations first pioneered in the RISC designs. As transistor counts soared in the late 1990s, the hardware overhead of translating the more complex x86 architecture became negligible. Figure 1.1 shows that the combination of architectural

advances of 120–140X are still much greater than their gains in latency of 4–8X. Clearly, bandwidth has outpaced latency across these technologies and will likely continue to do so. A simple rule of thumb is that bandwidth grows by at least the square of the improvement in latency. Computer designers should make plans accordingly. 10,000 Relative bandwidth improvement Microprocessor 1000 Network Disk Memory 100 (Latency improvement = bandwidth improvement) 10 1 1 10 100 Relative

of techniques, focusing on the important ideas first introduced in the 1980s and 1990s. In Chapter 5, we turn to the all-important area of memory system design. We will examine a wide range of techniques that conspire to make memory look infinitely large while still being as fast as possible. As in Chapters 2 through 4, we will see that hardware-software cooperation has become a key to highperformance memory systems, just as it has to high-performance pipelines. This chapter also covers virtual

exceptions. An exception is imprecise if the processor state when an exception is raised does not look exactly as if the instructions were executed sequentially in strict program order. Imprecise exceptions can occur because of two possibilities: 1. The pipeline may have already completed instructions that are later in program order than the instruction causing the exception. 2. The pipeline may have not yet completed some instructions that are earlier in program order than the instruction

Execute FP operation (RS[r].Qj = 0) and (RS[r].Qk = 0) Compute result: operands are in Vj and Vk Load-store step 1 RS[r].Qj = 0 & r is head of load-store queue RS[r].A ← RS[r].Vj + RS[r].A; Load step 2 Write Result FP operation or load Store ■ Load step 1 complete Read from Mem[RS[r].A] Execution complete at r & CDB available ∀x(if (RegisterStat[x].Qi=r) {Regs[x] ← result; RegisterStat[x].Qi ← 0}); ∀x(if (RS[x].Qj=r) {RS[x].Vj ← result;RS[x].Qj ← 0}); ∀x(if (RS[x].Qk=r) {RS[x].Vk ←

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